Patent attributes
A semiconductor device to which a stress technique is applied and in which a leakage current caused by silicidation can be suppressed. A gate electrode is formed over an element region defined by an isolation region formed in a semiconductor substrate with a gate insulating film between. Extension regions and source/drain regions are formed in the element region on both sides of the gate electrode. In addition, a semiconductor layer which differs from the semiconductor substrate in lattice constant is formed apart from at least part of the isolation region. By doing so, the formation of a spike near the isolation region is suppressed even if a silicide layer is formed. Accordingly, a leakage current caused by such a spike can be suppressed.
