Patent attributes
A ferroelectric memory includes a memory cell array including a first unit block, a second unit block, and a plurality of dummy cells. The plurality of dummy cells being arranged toward a column direction and being disposed between the first unit block and the second unit block. The first unit block including a plurality of first memory cells arranging in t rows, and including a plurality of first plate lines arranging toward a row direction. The second unit block including a plurality of second memory cells arranged in t rows, and including a plurality of second plate lines arranging toward a row direction. Each of the plurality of dummy cells including a ferroelectric capacitor. Either of the first second plate line or the second plate line of the second unit block extending above the plurality of dummy cells.
