Patent attributes
A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.
