US Patent 7996821 Data processor

A data processor having a debugging aid function capable of monitoring a plurality of kinds of internal buses from the outside and identifying each of the buses monitored is provided. A central processing unit (CPU), a debugging aid module, and other circuit modules are mounted on a semiconductor chip. The debugging aid module selects an information transmitting path in accordance with a trace condition from a plurality of information transmitting paths used for the operation of a central processing unit (CPU) or the like, holds trace information obtained according to the trace condition from the selected information transmitting path together with attribute information of the trace information in a buffer circuit, and outputs the information serially to the outside of the semiconductor chip. A plurality of kinds of internal buses can be monitored on the outside, and each of the buses monitored can be identified. The trace information and its attribute information is output serially from the same external terminal.