Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
August 16, 2011
Patent Application Number
11538815
Date Filed
October 5, 2006
Patent Primary Examiner
Patent abstract
A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.
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