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US Patent 7999304 Semiconductor device
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Patent
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Date Filed
February 6, 2008
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Date of Patent
August 16, 2011
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Patent Application Number
12026942
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Patent Citations Received
US Patent 11943924 Void formation for charge trap structures
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US Patent 11765903 Charge trap structure with barrier to blocking region
US Patent 11923407 Memory device including voids between control gates
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Patent Inventor Names
Akihito Yamamoto
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Daisuke Nishida
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Katsuaki Natori
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Katsuyuki Sekine
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Masayuki Tanaka
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Ryota Fujitsuka
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Yoshio Ozawa
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
7999304
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Patent Primary Examiner
Cuong Q Nguyen
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