US Patent 7999566 Wafer level testing

A wafer comprises a kerf region and a test chip. The kerf is a region in a wafer designated to be destroyed by chip dicing. The test chip is located within the kerf region and is configured to provide parametric data for a wafer fabrication process of a head. The test chip comprises a shield portion of a first shield layer electrically coupled to an element, a first pad within a second shield layer electrically coupled to the element, and a second pad within the second shield layer electrically coupled to the shield portion.