US Patent 7999588 Duty cycle correction circuitry

Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.