Patent attributes
A thin film transistor array panel includes a substrate, a gate line disposed on the substrate, and a capacitive electrode disposed on the substrate and separated from the gate line. The thin film transistor includes a data line intersecting the gate line, a thin film transistor connected to the gate line and the data line and including a drain electrode, and a coupling electrode connected to the drain electrode, overlapping the capacitive electrode, and having a through-hole disposed on the capacitive electrode. The thin film transistor includes a passivation layer disposed on the gate line, the data line, and the thin film transistor and having a contact hole that penetrates the through-hole and exposes the capacitive electrode, and a pixel electrode including a first subpixel electrode connected to the drain electrode and a second subpixel electrode connected to the capacitive electrode through the contact hole.
