Patent attributes
Embodiments of the present invention provide a system that maps an N-bit application to virtual memory. The N-bit application may be obtained by porting an M-bit application to an N-bit architecture where N is greater than M. During operation, the system receives a request to map an N-bit application to a computer's virtual memory. The system then maps the N-bit application to a section of virtual memory which begins at a memory address that is greater than or equal to 2M. If the N-bit application accesses a memory address which is less than 2M, the system can generate a trap, thereby facilitating the discovery of M-bit memory references in the N-bit application.