US Patent 8001492 Evaluation method for interconnects interacted with integrated-circuit manufacture
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Patent abstract
A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes.
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Patent Inventor Names
Wallace W. Lin0
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US Patent 08001492 Evaluation method for interconnects interacted with integrated-circuit manufacture US Patent 8001492 Evaluation method for interconnects interacted with integrated-circuit manufacture
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Patent Number
080014920
Patent Number
80014920
Edits on 27 Sep, 2022
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Is a
Patent Jurisdiction
Patent Number
080014920
Date of Patent
August 16, 2011
0Patent Application Number
122155520
Date Filed
June 27, 2008
0Patent Primary Examiner
Edits on 8 Dec, 2021
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US Patent 08001492 Evaluation method for interconnects interacted with integrated-circuit manufacture
Infobox
Is a
Patent jurisdiction
Patent number
08001492
Date of patent
August 16, 2011
Patent application number
12215552
Date Filed
June 27, 2008
Patent primary examiner
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