US Patent 8004904 Semiconductor integrated circuit device

A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a data line, and a power-on reset circuit (64) which starts an operation in response to power-on to reset a control circuit of the nonvolatile memory. The device further has a power-on precharge circuit (66) which starts an operation in response to the power-on to perform the precharge operation of the data line. The power-on reset circuit (64) includes a first CR operation circuit (642) which produces a reset release signal indicative of change of a voltage level at a time point when a first predetermined time period (T1) elapses from the power-on. The power-on precharge circuit (66) includes a second CR operation circuit (662) which produces a precharge completion signal indicative of change of a voltage level at a time point when a second predetermined time period (T2) elapses from the power-on. The first predetermined time period (T1) is longer than the second predetermined time period (T2).