Patent attributes
A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.
