Patent attributes
The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder 13 integrates the product of an information word D13 of six bits supplied from a cyclic shift circuit 12 and the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum D15 to a RAM 14. The RAM 14 stores the sum D15. Further, the RAM 14 successively reads out sums D16 of 2 bits stored already therein and supplies the read out sums D16 as sums D17 to an accumulator 16 through an interleaver 15. The accumulator 16 integrates the sums D17 and outputs a sum D18 obtained as a result of the integration as a parity bit p of a codeword c through a selector 17. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.
