Patent attributes
A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane.
