US Patent 8045074 Array substrate and display device

In the array substrate where the display region has the non-quadrangle shape, a sub-capacitance line which forms a sub-capacitance is disposed at the pixel, a intersection region of the scanning lead-out line and a signal lead-out line is located at the frame region on the outside of the display region, a common lead-out line which connects the sub-capacitance line in common is disposed at the frame region side where the scanning lead-out line is disposed, the common lead-out line is not disposed in the intersection region, but disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line.