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US Patent 8048723 Germanium FinFETs having dielectric punch-through stoppers

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
December 5, 2008
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Date of Patent
November 1, 2011
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Patent Application Number
12329279
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Patent Citations Received
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US Patent 12132111 Formation method of semiconductor device structure with gate stacks
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US Patent 11699758 Isolation structure having different distances to adjacent FinFET devices
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US Patent 11749720 Integrated circuit structure and method with solid phase diffusion
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US Patent 11749682 Selective dual silicide formation using a maskless fabrication process flow
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US Patent 11855151 Multi-gate device and method of fabrication thereof
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Patent Inventor Names
Chen-Nan Yeh
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Chen-Yi Lee
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Cheng-Hung Chang
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Shih-Ting Hung
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Yu-Rung Hsu
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Chen-Hua Yu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
8048723
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Patent Primary Examiner
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Brook Kebede
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