US Patent 8054695 Semiconductor memory apparatus

A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering an external data in accordance with the second external reference voltage.