US Patent 8116112 Semiconductor memory device

A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit.