Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Syota Miki0
Tadashi Arai0
Date of Patent
March 27, 2012
Patent Application Number
12276772
Date Filed
November 24, 2008
Patent Citations Received
Patent Primary Examiner
Patent abstract
An electronic component mounting package includes a structure (coreless substrate) in which a plurality of wiring layers are stacked one on top of another with insulating layers interposed therebetween and are interconnected through via holes formed in the insulating layers. The entire surface of the coreless substrate, exclusive of pad portions defined at desired positions of the outermost wiring layers thereof, is covered with a molding resin. Further, an interposer is mounted on the side of the electronic component mounting surface of the coreless substrate, and the molding resin is partially filled into a gap between the coreless substrate and the interposer.
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