Patent attributes
An integrated circuit includes a two-port static random access memory (SRAM) cell, which includes a first half write-port, a second half write-port, and a read-port. The first half write-port includes a first pull-up transistor, a first pull-down transistor, and a first pass-gate transistor interconnected to each other. The second half write-port includes a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor interconnected to each other and to the first half write-port. Channel lengths of the first pass-gate transistor and the second pass-gate transistor are less than channel lengths of the first pull-down transistor and the second pull-down transistor. The read-port includes a read-port pull-down transistor connected to the first half write-port, and a read-port pass-gate transistor connected to the read-port pull-down transistor.
