US Patent 8159265 Memory for metal configurable integrated circuits

Memory for a semiconductor device is disclosed. The memory array comprises: a memory cell replicated in rows and columns to form an array; and a plurality of first horizontal decode signals, each horizontal signal common to all the memory cells in a said row; and a plurality of first vertical decode signals, each vertical signal common to all the memory cells in a said column; wherein, said replicated memory cell further comprises: a storage device to store data; and a first decode device to receive a said first horizontal decode signal and a said first vertical decode signal and generate a first local decode signal to access a first unique memory cell in the array.