US Patent 8190825 Arithmetic processing apparatus and method of controlling the same
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Patent abstract
A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The common PFPORT secures an entry when the prefetch request loaded from the PFPORT into a L2 pipeline processing unit fails to be completed. The uncompleted prefetch request is loaded again from the common PFPORT to the L2 pipeline processing unit.
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Patent Inventor Names
Toru Hikichi0
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US Patent 08190825 Arithmetic processing apparatus and method of controlling the same US Patent 8190825 Arithmetic processing apparatus and method of controlling the same
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Patent Number
081908250
Patent Number
81908250
Edits on 28 Sep, 2022
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Patent Jurisdiction
Patent Number
081908250
Date of Patent
May 29, 2012
0Patent Application Number
128056910
Date Filed
August 13, 2010
0Patent Primary Examiner
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US Patent 08190825 Arithmetic processing apparatus and method of controlling the same
Infobox
Is a
Patent jurisdiction
Patent number
08190825
Date of patent
May 29, 2012
Patent application number
12805691
Date Filed
August 13, 2010
Patent primary examiner
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