US Patent 8203472 Compensation of clock jitter in analog-digital converter applications

Processes and systems for use in reducing clock jitter-induced error, obtain a first sample during each cycle of a periodic analog reference signal. The sample includes an error resulting at least in part from jitter-induced timing error of the clock signal. For each respective cycle, a second sample of a discrete-time analog representation of the periodic analog reference signal is also obtained. The second sample is substantially unsusceptible to jitter-induced timing error of the clock signal. Each of the first and second samples corresponds to the same respective cycle of the clock signal. For each cycle, a respective difference between each of the first and second samples is determined. The difference is indicative of timing error of the respective cycle of the clock signal. The difference is converted to a digital representation that can be used to compensate for jitter-induced error.