Patent attributes
When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.
