Patent attributes
A programmable logic device includes a plurality of logic blocks and a plurality of routing networks. One of the routing networks receives an output signal of one of the plurality of logic blocks and a master clock signal. The routing network includes a pre-charge driver which includes: a delayed clock signal generator generating a delayed clock signal which delays predetermined time from a master clock signal; a pre-charge drive signal generator which receives the output signal of the delayed clock signal generator and the master clock signal and outputs a pre-charge drive signal; an enable circuit which receives an output signal of the pre-charge drive signal generator and outputs a constant signal or the pre-charge drive signal; and an output circuit which receives an output signal of the enable circuit and the output signal of the logic block and outputs one.
