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US Patent 8361842 Embedded wafer-level bonding approaches

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
September 13, 2010
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Date of Patent
January 29, 2013
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Patent Application Number
12880736
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Patent Citations Received
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US Patent 12131984 Heterogeneous fan-out structure and method of manufacture
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US Patent 12119235 Methods of manufacture of semiconductor devices having redistribution layer using dielectric material having photoactive component
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US Patent 12119320 Chip package structure with bump
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US Patent 12125797 Package structure with fan-out feature
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US Patent 12125820 Through-dielectric vias for direct connection and method forming same
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US Patent 12132004 Semiconductor devices and methods of manufacture
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US Patent 11749644 Semiconductor device with curved conductive lines and method of forming the same
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US Patent 11756802 Thermally conductive material in the recess of an encapsulant and sidewall of an integrated circuit device
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US Patent 11756931 Chip package structure with molding layer
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US Patent 11769718 Packages with Si-substrate-free interposer and method forming same
•••
Patent Inventor Names
Chen-Hua Yu
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Jing-Cheng Lin
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
8361842
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Patent Primary Examiner
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Peniel M Gumedzoe
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