Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Ian P. Shaeffer0
Date of Patent
February 19, 2013
0Patent Application Number
128086620
Date Filed
January 7, 2009
0Patent Citations Received
Patent Primary Examiner
Patent abstract
A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.
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