US Patent 8384453 Frequency adjustment in a control system

The present disclosure relates to a method, apparatus, and system for locking a phase locked loop (PLL). The method may include receiving a reference signal at a phase locked loop (PLL) circuitry having a first PLL circuitry and a second PLL circuitry. The first PLL circuitry may include a fixed frequency oscillator. The method may further include adjusting a division ratio using, at least in part, a fractional divider circuitry in communication with the fixed frequency oscillator, to generate a feedback signal having a substantially equal frequency and a substantially equal phase in relation to a reference frequency. The method may also include receiving the feedback signal and the reference frequency at a phase detector.