Patent attributes
A method, apparatus and computer program for measuring a latency associated with a transaction between logic units is described. In certain described examples, transactions take place over an on-chip interconnect, for example an interconnect forming part of a system-on-chip configuration. In certain described examples, time values obtained in response to signals indicative of transaction initiation events are added to a data queue. A transaction initiation event has an associated transaction identifier and each data queue is associated with a particular transaction identifier. The method and apparatus enable time values relating to transactions that overlap in time to be output from a data queue on receipt of a transaction completion event and thus measured.
