Patent attributes
A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register, a low threshold register, and a high threshold register. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action.
