US Patent 8412668 Offline formal verification of executable models

A system and method for automatic formal verification of an executable system includes an assertion monitor configured to verify a system against an assertion in the specification. The assertion monitor includes a parser configured to generate a propositional formula representing an assertion in the specification using Boolean propositions, a filter configured to generate a trace of truth assignments for the propositional symbols and a trace verifier configured to verify the assertion using the trace of truth assignments for the propositional symbols and the propositional formula.