Patent attributes
Provided is a gate signal line driving circuit including: 2n clock signal lines where 2n-phase clock signals are input in the normal order of the sequence in normal-directional scanning and in the inverse order of the sequence in inverse-directional scanning, respectively; and a plurality of basic circuits, each being connected with the 2n clock signal lines and outputting a gate signal from an output terminal, in which each of the basic circuits includes a high-voltage applying switching circuit where one clock signal line is connected to an input side and applies a voltage applied to the clock signal line to the output terminal and an off-signal applying switching circuit that applies an off-voltage to a switch of the high-voltage applying switching circuit, and a clock signal line where a clock signal having an inverse phase is connected to a switch of the off-signal applying switching circuit.
