Patent attributes
CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.
