US Patent 8463835 Circuit for and method of providing a floating-point adder

A floating-point adder circuit is described. The circuit comprises an input multiplexer coupled to receive a first input value and a second input value; an adder-subtractor circuit selectively coupled to receive one of the first input value and the second input value at each of a first input and a second input, wherein the value coupled to the second input is added to or subtracted from the value coupled to the first input; a right shift circuit for aligning the smaller of the first input value and the second input value which is coupled to the second input of the adder-subtractor circuit; and an additional shift circuit (e.g., a left shift/right shift circuit of a combined near path and far path) coupled to the output of the adder-subtractor circuit. A method of implementing a floating-point adder is also disclosed.