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US Patent 8546955 Multi-die stack package

Patent 8546955 was granted and assigned to Xilinx on October, 2013 by the United States Patent and Trademark Office.

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Patent attributes

Current Assignee

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Date of Patent

October 1, 2013

Patent Application Number

13587716

Date Filed

August 16, 2012

Patent Citations Received

US Patent 12125833 Integrated circuit package and method forming same

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US Patent 12079475 Ferroelectric memory chiplet in a multi-dimensional packaging

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US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

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US Patent 12119335 Interconnection structures for high bandwidth data transfer

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US Patent 11694940 3D stack of accelerator die and multi-core processor die

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US Patent 11749610 Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

US Patent 11764190 3D stacked compute and memory with copper pillars

US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond

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