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US Patent 8546956 Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Date of Patent

October 1, 2013

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Patent Application Number

138268300

Date Filed

March 14, 2013

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Patent Citations Received

US Patent 12136562 3D semiconductor device and structure with single-crystal layers

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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells

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US Patent 12120880 3D semiconductor device and structure with logic and memory

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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells

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US Patent 11694922 Multilevel semiconductor device and structure with oxide bonding

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US Patent 11694944 3D semiconductor device and structure with metal layers and a connective path

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US Patent 11711928 3D memory devices and structures with control circuits

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US Patent 11763864 3D memory semiconductor devices and structures with bit-line pillars

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Patent Primary Examiner

Peniel M Gumedzoe

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