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US Patent 8612809 Systems, methods, and apparatuses for stacked memory

Patent 8612809 was granted and assigned to Intel on December, 2013 by the United States Patent and Trademark Office.

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Date of Patent

December 17, 2013

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Patent Application Number

126555900

Date Filed

December 31, 2009

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Patent Citations Received

US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

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US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging

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US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

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US Patent 12079475 Ferroelectric memory chiplet in a multi-dimensional packaging

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US Patent 11764190 3D stacked compute and memory with copper pillars

US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond

US Patent 11791233 Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

US Patent 11836102 Low latency and high bandwidth artificial intelligence processor

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