US Patent 8637912 Vertical gate device with reduced word line resistivity

A semiconductor device includes a substrate having a primary side. A first pillar extends vertically with respect to the primary side of the substrate, the first pillar defining first and second conductive regions and a channel region that is provided between the first and second conductive regions. A first gate is provided over the channel region of the first pillar. A buried word line extends along a first direction below the first pillar, the buried word line configured to provide a first control signal to the first gate. A first interposer is coupled with the buried word line and the first gate to enable the first control signal to be applied to the first gate via the buried word line.