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US Patent 8652894 Method for fabricating a FinFET device
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Patent
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Date Filed
November 9, 2012
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Date of Patent
February 18, 2014
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Patent Application Number
13673406
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Patent Citations Received
US Patent 12087861 FinFETs and methods of forming FinFETs
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US Patent 12009399 Semiconductor device suppressing rounded shapes of source/drain contact layers
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US Patent 12062692 Tapered dielectric layer for preventing electrical shorting between gate and back side via
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US Patent 12068191 Low-resistance contact plugs and method forming same
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US Patent 12075607 Semiconductor device
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US Patent 11682710 Structure and formation method of semiconductor device structure with gate structure
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US Patent 11699758 Isolation structure having different distances to adjacent FinFET devices
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US Patent 11749682 Selective dual silicide formation using a maskless fabrication process flow
US Patent 11764220 Method of manufacturing a semiconductor device by patterning a serpentine cut pattern
US Patent 11764286 Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
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Patent Inventor Names
Chien-Chang Su
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Hsien-Hsin Lin
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Tsz-Mei Kwok
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
8652894
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Patent Primary Examiner
Jae Lee
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