US Patent 8659909 Method for reducing loadline impedance in a system
Patent 8659909 was granted and assigned to Intel on February, 2014 by the United States Patent and Trademark Office.
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Patent abstract
In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.
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Patent Inventor Names
Damion Searls0
Edward Osburn0
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Official Website
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US Patent 08659909 Method for reducing loadline impedance in a system US Patent 8659909 Method for reducing loadline impedance in a system
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Patent Number
086599090
Patent Number
86599090
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Is a
Current Assignee
Patent Jurisdiction
Patent Number
086599090
Date of Patent
February 25, 2014
0Patent Application Number
115886820
Date Filed
October 27, 2006
0Official Website
Patent Primary Examiner
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US Patent 08659909 Method for reducing loadline impedance in a system
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
08659909
Date of patent
February 25, 2014
Patent application number
11588682
Date Filed
October 27, 2006
Patent primary examiner
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