US Patent 8689157 Extracting capacitance and resistance from FinFET devices

Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.