US Patent 8730740 Semiconductor memory device

According to one embodiment, a semiconductor memory device includes units each including memory cells, a data bus connected to each of the units and having data lines, holding circuits configured to hold fail information supplied from the unit through the data bus as a verify result after writing data, and provided in association with the data lines, respectively, daisy chain circuits configured to shift a flag includes a logical sum of the fail information held in the holding circuits, and provided in association with the data lines, respectively, and a search circuit configured to search for fail bits in the units based on the flag.