US Patent 8737676 Defect estimation device and method and inspection system and method

Acquired mask data of a defect portion is sent to a simulated repair circuit 300 to be simulated. The simulation of the acquired mask data 204 is returned to the mask inspection results 205 and thereafter sent to a wafer transfer simulator 400 along with a reference image at the corresponding portion. A wafer transfer image estimated by the wafer transfer simulator 400 is sent to a comparing circuit 301. When it is determined that there is a defect in the comparing circuit 301, the coordinates and the wafer transfer image which is a basis for the defect determination are stored as transfer image inspection results 206. The mask inspection results 205 and the transfer image inspection result 206 are then sent to the review device 500.