US Patent 8739103 Techniques for placement in highly constrained architectures
Patent 8739103 was granted and assigned to Cypress Semiconductor Corporation on May, 2014 by the United States Patent and Trademark Office.
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Techniques for placement in highly constraint chip architectures are described herein. In an example embodiment, a computer system places a digital portion of an electronic design for a programmable chip. The programmable chip comprises multiple fixed-function blocks and a plurality of pins, where each one of the multiple fixed-function blocks can be coupled only to a respective subset of the plurality of pins. The electronic design comprises a particular fixed-function block (FFB) instance that is connected to a particular input-output (IO) instance. The computer system places (e.g., by using a backtracking search) the particular FFB instance on a particular fixed-function block and the particular IO instance on a particular pin from a particular subset of the plurality of pins, where in the programmable chip the particular fixed-function block can be coupled only to the particular subset of the plurality of pins.
US Patent 08739103 Techniques for placement in highly constrained architectures US Patent 8739103 Techniques for placement in highly constrained architectures
US Patent 08739103 Techniques for placement in highly constrained architectures
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