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US Patent 8836141 Conductor layout technique to reduce stress-induced void formations

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Is a

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Min-Hwa Chi0

Tai-Chun Huang0

Chih-Hsiang Yao0

Date of Patent

September 16, 2014

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Patent Application Number

138698440

Date Filed

April 24, 2013

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Patent Citations Received

US Patent 12089390 Cell manufacturing

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US Patent 11792969 Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM

US Patent 11804487 Source/drain regions of semiconductor devices and methods of forming the same

US Patent 11842131 Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells

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US Patent 11935833 Method of forming power grid structures

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US Patent 11978732 Methods of manufacturing semiconductor devices

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US Patent 11990511 Source/drain device and method of forming thereof

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US Patent 11714946 Standard cell and semiconductor device including anchor nodes and method of making

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Patent Primary Examiner

Fernando L Toledo

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