US Patent 8866520 Phase-locked loop architecture and clock distribution system

Patent 8866520 was granted and assigned to Altera on October, 2014 by the United States Patent and Trademark Office.

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Patent

Patent attributes

Patent Applicant

Altera

Current Assignee

Altera

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

88665200

Patent Inventor Names

Richard G. Cliff0

Sergey Shumarayev0

Tien Duc Pham0

Date of Patent

October 21, 2014

Patent Application Number

140231740

Date Filed

September 10, 2013

Patent Citations Received

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US Patent 11757609 Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence

Patent Primary Examiner

‌

Brandon S Cole

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