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US Patent 8928119 Three dimensional structure memory

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8928119
Date of Patent
January 6, 2015
Patent Application Number
12405240
Date Filed
March 17, 2009
Patent Citations Received
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
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US Patent 12120880 3D semiconductor device and structure with logic and memory
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
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US Patent 11711928 3D memory devices and structures with control circuits
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US Patent 11784082 3D semiconductor device and structure with bonding
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US Patent 11784169 3D semiconductor device and structure with metal layers
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US Patent 11804396 Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
...
Patent Primary Examiner
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Zandra Smith
Patent abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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