US Patent 8936976 Conductivity improvements for III-V semiconductor devices
Patent 8936976 was granted and assigned to Intel on January, 2015 by the United States Patent and Trademark Office.
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Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
US Patent 08936976 Conductivity improvements for III-V semiconductor devices US Patent 8936976 Conductivity improvements for III-V semiconductor devices
US Patent 08936976 Conductivity improvements for III-V semiconductor devices
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