US Patent 9099444 3D integrated circuit package with through-mold first level interconnects
Patent 9099444 was granted and assigned to Intel on August, 2015 by the United States Patent and Trademark Office.
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3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
US Patent 09099444 3D integrated circuit package with through-mold first level interconnects US Patent 9099444 3D integrated circuit package with through-mold first level interconnects
US Patent 09099444 3D integrated circuit package with through-mold first level interconnects
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